vhdl同时检测两个信号上升沿中，您说设置一个时钟信号clock，请问如何设置时钟信号
按第一个按键则数码管数字加一，按第二个按键则数码管数字减一，按第三个则数字左移，在最右边输入add_outside: process(clk,reset_all) --key1:按键加一
begin
if(key1'event and key1='0') then
key1_clear <= '1';
case location is
when "00" => bit_one_out <= bit_one_out + 1;
if(bit_one_out = 9) then
bit_one_out <= 0;
end if;
when "01" => bit_two_out <= bit_two_out + 1;
if(bit_two_out = 9) then
bit_two_out <= 0;
end if;
when "10" => bit_three_out <= bit_three_out + 1;
if(bit_three_out = 9) then
bit_three_out <= 0;
end if;
when "11" => bit_four_out <= bit_four_out + 1;
if(bit_four_out = 9) then
bit_four_out <= 0;
end if;
end case;
end if;
end process add_outside;
sub_outside: process(clk,reset_all) --key2
begin
if(key2'event and key2='0') then
key2_clear <= '1';
case location is
when "00" => bit_one_out <= bit_one_out - 1;
if(bit_one_out = 0) then
bit_one_out <= 9;
end if;
when "01" => bit_two_out <= bit_two_out - 1;
if(bit_two_out = 0) then
bit_two_out <= 9;
end if;
when "10" => bit_three_out <= bit_three_out - 1;
if(bit_three_out = 0) then
bit_three_out <= 9;
end if;
when "11" => bit_four_out <= bit_four_out - 1;
if(bit_four_out = 0) then
bit_four_out <= 9;
end if;
end case;
end if;
end process sub_outside;
此程序出错，不可以在两个进程对同一个赋值
